1. Technical Field
This disclosure relates to semiconductor devices that include capacitors and methods of fabricating the same.
2. Description of the Related Art
As the integration scale of semiconductor devices increases, the cell sizes of semiconductor devices such as Dynamic Random Access Memories (DRAMs) decrease. Consequently, the effective area of a lower electrode in a cell capacitor also decreases. However, a certain level of cell capacitance is generally required for proper device operation.
One approach to achieving a high level of cell capacitance within a limited area is the use of high-k dielectric materials, which have dielectric constants that are several times to several hundreds times higher than those materials that are commonly used as a capacitor dielectric layer, such as oxide/nitride/oxide (ONO).
A disadvantage to the above approach is that a doped polysilicon electrode used as a top/bottom electrode of a conventional capacitor typically reacts with the high-k dielectric layer, degrading the electrical characteristics of the capacitor. Thus, a low-k dielectric layer such as a silicon oxynitride (SiON) layer is typically formed between the doped polysilicon electrode and the high-k dielectric layer.
The presence of the additional low-k dielectric layer increases the thickness of the capacitor dielectric layer. Another disadvantage of using the conventional doped polysilicon electrode is that the doped polysilicon layer needs to be formed at above 600° C. to activate dopants of the polysilicon electrode or a specific thermal treatment is often required. This high temperature process increases leakage currents in the capacitor.
As alternatives to using semiconductor-insulator-semiconductor (SIS) capacitors, which implement the top and bottom electrodes using doped polysilicon layers, it has been suggested that metal layers, which have a reactivity that is relatively lower than that of the polysilicon layers, be used. A metal layer may be used as a top electrode in conjunction with a high-k dielectric layer, or a metal layer may be used to implement both the top electrode and the bottom electrode. The former and latter capacitors are known as a metal-insulator-semiconductor (MIS) capacitor and a metal-insulator-metal (MIM) capacitor, respectively.
For MIS capacitors, there may be limitations in integration processes related to wet etching, dry etching, and stress. Also, since the metal layer has a low resistivity, the metal layer may not be adequate to function as a resistor layer for delaying signals.
Regardless of the capacitor type, in order to decrease the capacitor leakage current while simultaneously achieving highly integrated DRAM cells, it is often necessary to perform processes subsequent to formation of the high-k dielectric layer at a low temperature because the thermal stability of the high-k dielectric layer is not very good. Also, when an interconnection process is performed after the capacitor formation process, it is often required to decrease a contact resistance level between the top electrode of the capacitor and a metal contact plug.
Embodiments of the invention address these and other limitations of the conventional art.